Semiconductor memories are commonly used in several applications for storing information, temporarily, in the so-called volatile memories, or permanently, in the so-called non-volatile memories, which are able to preserve the information also in absence of power supply. Typically, a non-volatile semiconductor memory comprises a matrix of memory cells, for example, floating-gate MOSFETs; each memory cell has a threshold voltage which is programmed to different levels, to which respective logic values correspond.
A very common type of memory is the so-called flash memory, which, in addition to the non-volatility, offers the possibility of electrically writing and erasing the memory cells.
For example, in the bi-level flash memories, wherein each cell is adapted to store only one information bit, in an erased condition the generic memory cell has a relatively low threshold voltage (the logic value 1 is typically associated thereto); the cell is programmed by the injection of electrons into the floating gate thereof: in such a condition the memory cell has a higher threshold voltage (the logic value 0 is typically associated thereto). In multi-level flash memories, each memory cell is adapted to store more than one information bit, and it can be programmed at a selected one of a plurality of different states, to which respective values of the threshold voltage correspond. For example, in a memory which operates with four levels (a so-called four-level memory), each memory cell stores a logic value which includes two information bits (that is, 11, 10, 01 and 00, as the threshold voltage of the memory cell increases).
For retrieving the stored information, the semiconductor memories comprise reading circuitries adapted to read the data stored in the memory cells.
In particular, the logic values stored in the selected memory cells are read by comparing a current flowing through each memory cell with the currents provided by one or more reference cells, programmed in a predetermined condition.
For this purpose, the reading circuitry also applies a suitable biasing voltage to the selected memory cells and the reference cells.
The comparison operation between the currents flowing respectively through the selected memory cell and the reference cells is typically performed by sense amplifiers, included in the reading circuitry and adapted to provide an indication of the stored logic value depending on the output voltage thereof.
A sense amplifier used in semiconductor memories is disclosed in the European patent application No. 03017939.4, which is incorporated by reference. Such a sense amplifier uses a negative feedback control loop in order to control and stabilize the voltage of an access line to the selected memory cell during the reading operations. In particular, two differential amplifiers are provided, the first amplifier being inserted in a negative feedback loop by means of a resistor which is connected between the inverting input terminal and the output terminal thereof, while the second amplifier is adapted to sense the voltage variation across the resistor and, based on the sensed voltage variations, to provide an indication of the data stored in the selected memory cell.
It has been observed that such structure, advantageous under many viewpoints, has however the drawback that the resistor occupies a significant area of the semiconductor material chip wherein the sense amplifier is integrated.
The problem may become larger as the number of sense amplifiers which have to be integrated in the memory increases. For example, in the case of flash memories, wherein distinct individually-erasable memory sectors are often provided for, for each partition (or set) of sectors (for example, 16 memory sectors) a plurality of sense amplifiers is provided. In general, as the memory partitioning into sets of memory cells to be read concurrently increases, the number of sense amplifiers increases, and thus the area of the semiconductor chip dedicated to sense amplifiers becomes substantial.
In other words, the occupation of semiconductor area by the reading circuitry is more and more a limiting aspect in semiconductor memories which require a high number of sense amplifiers during the reading operations, contrasting the desire to increasingly minimize the memory-area-to-data-storage-capacity ratio.
Moreover, the resistor integrated in the sense amplifier of the above-mentioned patent application may have a high sensitivity to temperature variations (that is, as the temperature varies, the value of its resistance varies significantly) and this can make the read data uncertain.